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Power Supply IC Series for TFT-LCD Panels
12V Input Multi-channel System Power Supply IC
BD8160AEFV
No.09035EBT01
Description The BD8160AEFV is a system power supply for the TFT-LCD panels used for liquid crystal TVs. Incorporates two high-power FETs with low on resistance for large currents that employ high-power packages, thus driving large current loads while suppressing the generation of heat. A charge pump controller is incorporated as well, thus greatly reducing the number of application components. Features 1) Step-up and step-down DC/DC converter 2) Incorporates 2.6 A N-channel FET. 3) Incorporates positive/negative charge pumps. 4) Input voltage limit: 8 V to 18 V 5) Feedback voltage: 1.162 V 1% 6) Switching frequency: 500 kHz / 750kHz 7) Protection circuit: Under voltage lockout protection circuit Thermal shutdown circuit Overcurrent protection circuit Short Circuit Protection Overvoltage protection circuit for VS voltage (Boost DC/DC output) 8) HTSSOP-B28 Package Applications Power supply for the TFT-LCD panels used for LCD TVs Absolute maximum ratings (Ta = 25C) Parameter Supply Voltage Power Dissipation Operating Temperature Range Storage Temperature Range Junction Temperature SW Voltage SWB Voltage EN1,EN2 Voltage
Symbol SUP,VIN Pd Topr Tstg Tjmax VSW VSWB VEN1,VEN2
Rating 20 4700* -40+85 -55+150 150 21 19 19
Unit V mW V V V
* Derating in done 37.6mW/ for operating above Ta25(On 4-layer 70.0mmx70.0mmx1.6mm board)
Recommendable Operation Range (Ta=25) Parameter Supply Voltage VS Voltage Switch current for SW Switch current for SWB EN1,EN2,FREQ Voltage
** Pd, ASO should not be exceeded
Symbol SUP,VIN VS ISW ISWB VEN1,VEN2,VFREQ
Limits Min 8 VIN+2 Typ 12 15 Max 18 18 2.6** 2.0** 18
Unit V V A A V
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1/18
2009.07 - Rev.B
BD8160AEFV
Electrical characteristics (unless otherwise specified VIN=12V and Ta=25C) 1. DC/DC converter controller block Parameter Soft start - SS SS source current Error amplifier block - FB and FBB FB and FBB input bias current Feedback voltage for boost converter Feedback voltage for buck converter SW block - SW On resistance N-channel Leak current N-channel Switch current limit for SW Maximum duty cycle SW block - SWB On resistance N-channel Leak current N-channel Switch current limit for SWB Protections Over Voltage Protection for SW 2. Charge pump driver block Parameter Error amplifier block - FBP and FBN FBP, FBN input bias current Feedback voltage for VGH Feedback voltage for VGL Delay start block DLY1, DLY2 source current DRP, DRN block On resistance N-channel On resistance P-channel RONN RONP 5 3 IO=20mA IO=20mA IDLY1, IDLY2 2 5 9 A IFBP, IFBN VFBP VFBN 1.188 0.18 0.1 1.213 0.2 1 1.238 0.22 A V V Symbol Limits Min Typ Max Unit VSWOVP 18.5 19 19.5 V RONH ILEAKN2 ISWB 2.0 0.2 0 0.3 10 A A IO=0.8A RONN ILEAKN1 ISW
MDUTY
Technical Note
Symbol
Limits Min Typ Max
Unit
Conditions
ISO
6
10
14
A
VSS=0.5V
IFB12 VFB VFBB
1.150 1.188
0.1 1.162 1.213
2 1.174 1.238
A V V Voltage follower
2.6 75
0.2 0 90
0.3 10 97
A A %
IO=0.8A VSW =18V
FB= 0V
VINB=18V , VSWB =0V
Conditions
VDLY=0.5V
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2/18
2009.07 - Rev.B
BD8160AEFV
Electrical characteristics (unless otherwise specified VIN=12V and Ta=25C) 3. General Parameter Supply current Average supply current Oscillator Oscillation frequency1 Oscillation frequency2 Protections Under voltage lockout threthold1 Under voltage lockout threthold2 Thermal Shutdown Short Circuit Protection Time 1 Short Circuit Protection Time 2 FB threshold1 for SCP FB threshold2 for SCP FBB threshold1 for SCP FBB threshold2 for SCP FBP threshold1 for SCP FBP threshold2 for SCP FBN threshold1 for SCP FBN threshold2 for SCP Reference Voltage Reference Voltage Gate Drive Gate drive threshold GD output low voltage GD output leakage current Logic signals EN1, EN2, FREQ High level input voltage Low level input voltage VIH VIL 2.0 0.8 V V VGD VOL ILK 0.985 1.065 0.7 0 1.145 1.4 10 V V A I=1mA VREF 1.188 1.213 1.238 V VUVLO1 VUVLO2 TTSD TSCP1 TSCP2 VFBSCP1 VFBSCP2 VFBBSCP1 VFBBSCP2 VFBPSCP1 VFBPSCP2 VFBNSCP1 VFBNSCP2 6.9 6.5 153 230 0.985 7.4 7.0 175 219 328 1.065 0.969 1.055 0.874 0.967 0.859 0.406 0.505 7.9 7.5 285 426 1.145 V V ms ms V V V V V V V V VIN rising FOSC1 FOSC2 600 400 750 500 900 600 kHz kHz ICC 5 8 mA Symbol Limits Min Typ Max Unit
Technical Note
Conditions
FREQ = High FREQ = low
VIN falling *1 FREQ = High FREQ = Low FB rising FB falling FBB rising FBB falling FBP rising FBP falling FBN falling FBN rising
* This product is not designed for protection against radioactive rays.
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3/18
2009.07 - Rev.B
BD8160AEFV
Reference Data (Unless otherwise specified, Ta = 25C)
5 700 600 4.8 500 ISUP uA 400 300 200 4.2 100 -8 4 8 10 12 VIN : [V] 14 16 18 0 8 10 12 VIN : [V] 14 16 18 -10 8 10 ISTB uA 4.6 Icc [mA] 10 8 6 4 2 0 -2 -4 -6
Technical Note
4.4
12
14
16
18
AVIN : [V]
Fig.1 SUPPLY CURRENT
1.217 1.216 1.215 1.214 REF [V] 1.213 1.212 1.211 1.210 1.209 1.208 1.207 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 T a : [] 200 100 0 f [kHz] 600 500 400 300 800 700
Fig.2 SUPPLY CURRENT
12
Fig.3 STANDBY CURRENT
750 kHz
11.5
Iss [uA]
500 kHz
11
10.5
10 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 Ta : [] -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 T a : []
Fig.4 REF VOLTAGE
7 6.8 6.6 6.4 IDLY [uA] IFB [uA] 6.2 6 5.8 5.6 5.4 5.2 5 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80
Fig.5 SWITCHING FREQUENCY
0.1 0.08 0.06 0.04 IFB [uA] 0.02 0 -0.02 -0.04 -0.06 0 0.5 1 V FB, V FBB [V] 1.5 2 0.1 0.08 0.06 0.04 0.02 0 -0.02 -0.04 -0.06 -0.08 -0.1
Fig.6 SS SOURCE CURRENT
0
0.5
1 V FBP, VFBN [V]
1.5
2
Ta : []
Fig.7 DLY1,2 SOURCE CURRENT
Fig.8 INPUT BIAS CURRENT
Fig.9 INPUT BIAS CURRENT
2.5 14 2 12 10 DLY1 V 8 6 4 0.5 2 0 0 0.5 1 VEN1 V 1.5 2 0 0 0.5 1 VEN2 [V] 1.5 2
Ron []
0.3
0.25 0.2
Vs [V]
1.5
0.15
1
0.1 0.05
0 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 T a []
Fig.10 EN1 THRESHOLD VOLTAGE
Fig.11 EN2 THRESHOLD VOLTAGE
Fig.12 SW ON RESISTANCE
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4/18
2009.07 - Rev.B
BD8160AEFV
Reference Data (Unless otherwise specified, Ta = 25C)
0.3 4.5 4 0.25 3.5 0.2 Ron [] Ron [] 3 2.5 2 1.5 1 0.05 0.5 0 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 T a [] 0 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 T a [] Ron [] 3.5 3 2.5 2 1.5 1 0.5 0 -40 -30 -20 -10 0 4.5 4
Technical Note
0.15
0.1
10 20
30 40 50 60 70 80
T a []
Fig.13 SWB ON RESISTANCE
Fig.14 DRP ON RESISTANCE
Fig.15 DRN ON RESISTANCE
100 95
500kHz 750kHz
EFFICIENCY [%]
100 98 96 94 92 90 88 86 84 82 80
VS
EFFICIENCY [%]
90 85 80 75 70 65 60 55 50 0 0.2 0.4
500kHz 750kHz
SW
0.6
0.8
1 Iout [A]
1.2
1.4
1.6
1.8
2
8
9
10
11 VIN [V]
12
13
14
Fig.16 OVP WAVEFORM
Fig.17 STEP UP EFFICIENCY
Fig.18 STEP UP EFFICIENCY
100 90 80 EFFICIENCY [%] 70 60 50 40 30 20 10 0 0
500kHz 750kHz
EFFICIENCY [%]
100 90 80 70 60 50 40 30 20 10 0
500kHz 750kHz
VS Vlogic VGH VGL
0.2
0.4
0.6
0.8
1 Iout [A]
1.2
1.4
1.6
1.8
2
8
9
10
11 VIN [V]
12
13
14
Fig.19 STEP DOWN EFFICIENCY
Fig.20 STEP DOWN EFFICIENCY
Fig.21 START UP WAVEFORM
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5/18
2009.07 - Rev.B
BD8160AEFV
Block Diagram
AVIN
UVLO TSD
Technical Note
OS
PG OVP OCP
CURRENT SENSE
GD
VREG
REF FREQ SS
VREF OSC SOFT START
S EN2 DRV R CURRENT SENSE
SW SW PGND
SLOPE
PWM
FB COMP
ERR
OCP
S EN1 DRV R
VINB VINB SWB
SLOPE
SOFT START
PWM
BOOT SUP
DETECTOR Short Circuit Protection
FBB EN1
ERR
FB FBB FBP FBN
EN2
POSITIVE CHARGE PUMP
PG SUP
FBP
ERR
DRP
EN2
SUP
FBN
IDLY
NEGATIVE CHARGE PUMP IDLY 1 IDLY
DRN
DLY 1 DLY 2
IDLY 2
Fig.22 Block Diagram Typical Application
VIN 12V Boostout
C40 4*10F C18 1F L1 10H
GND
D2 RSX501
Q1 RSQ035P0 3 R5 120k R6 10k R12 47k C28 3*10F D4D6 DAN217U C23 0.1F R15 47k C27 0F
Vs 15V/1.5A
C21 20F
8 12 20 21 22 16
SUP FREQ VINB VINB AVIN EN1 EN2 DRN FBN REF PGN PGN SS DLY1
SW SW FB OS GN GD DRP FBP BOOT SW NC FBB COMP DLY2
4 5 1 3 23 27 10 14 17 18 19 15 2 26
C4 0.1F
C6 120pF
R2 0
VGL -5V/50mA
R3 51k R4 10k C9 0.047F
D4D5 DAN217U
C2 0.022
9 11 13 24 6 7 28 25
C14
0.1 F R9 22k R10 1k C22 4.7F
VGH 28V/50mA
C8 4.7F
C1 2200pF
C11 0.1F
R1 7.5k L2 10H D1 R7 200k R8 115k C15 68pF
C3 0.1F
C5 0.047F
VLOGIC 3.3V/1.5A
C12 4*10F
RSX501
EN1 terminal should be pulled-up to VIN terminal.
Fig.23 Typical Application
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6/18
2009.07 - Rev.B
BD8160AEFV
Pin Assignment Diagram BOOT DLY2 DLY1 VINB VINB SWB AVIN GND REF N.C. EN1 FBB GD
Technical Note
SS
SUP
COMP
EN2
PGND
PGND
FREQ
OS
FB
Fig. 24 Pin Assignment Diagram Pin Assignment and Pin Function Pin No. Pin name Function 1 2 3 4 5 6 7 8 9 10 11 12 13 14 FB COMP OS SW SW PGND PGND SUP EN2 DRP DRN FREQ FBN FBP Feedback input 1 for VS Error amp output Output sense pin Switching pin for VS Switching pin for VS Ground pin Ground pin Power supply input pin Enable pin for VS and VGH Switching pin for VGH Switching pin for VGL Frequency Feedback input 1 for VGL Feedback input 1 for VGH
Pin No. Pin name 15 16 17 18 19 20 21 22 23 24 25 26 27 28 FBB EN1 BOOT SWB N.C. VINB VINB AVIN GND REF DLY1 DLY2 GD SS
DRN
DRP
FBN
FBP
SW
SW
Function Feedback input for Vlogic Enable pin for Vlogic and VGL Capacitance connection pin for booting Switching pin for Vlogic Non-connect pin Power supply input pin Power supply input pin Power supply input pin Analog Ground pin Internal reference output pin Delay start capacitance connection pin for VGL Delay start capacitance connection pin for VS Gate drive pin for load switch Soft start capacitance connection pin for VS
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7/18
2009.07 - Rev.B
BD8160AEFV
Block Operation VREG A block to generate constant-voltage for DC/DC boosting. VREF A block that generates internal reference voltage of 2.9 V (Typ.).
Technical Note
TSD/UVLO TSD (Thermal shutdown)/UVLO (Under Voltage Lockout) protection block. The TSD circuit shuts down IC at 175C (Typ.) The UVLO circuit shuts down the IC when the Vcc is 7 V (Typ.) or below. Error amp block (ERR) This is the circuit to compare the reference voltage and the feedback voltage of output voltage. The COMP pin voltage resulting from this comparison determines the switching duty. At the time of startup, since the soft start is operated by the SS pin voltage, the COMP pin voltage is limited to the SS pin voltage. Oscillator block (OSC) This block generates the oscillating frequency. SLOPE block This block generates the triangular waveform from the clock created by OSC. Generated triangular waveform is sent to the PWM comparator. PWM block The COMP pin voltage output by the error amp is compared to the SLOPE block's triangular waveform to determine the switching duty. Since the switching duty is limited by the maximum duty ratio which is determined internally, it does not become 100%. DRV block A DC/DC driver block. A signal from the PWM is input to drive the power FETs. CURRENT SENSE Current flowing to the power FET is detected by voltage at the CURRENT SENSE and the overcurrent protection operates at 2.0/2.6A (min.). When the overcurrent protection operates, switching is turned OFF and the SS pin capacitance is discharged. DELAY START A start delay circuit for positive/negative charge pump and Boost converter. Soft start circuit Since the output voltage rises gradually while restricting the current at the time of startup, it is possible to prevent the output voltage overshoot or the rush current. Positive charge pump A controller circuit for the positive-side charge pump. The switching amplitude is controlled so that the feedback voltage FBP will be set to 1.213 V (Typ.). The start delay time can be set in the DLY2 pin at the time of startup. When the DLY2 voltage reaches 0.65 V (Typ.), switching waves will be output from the DRP pins. Negative charge pump A controller circuit for the negative-side charge pump. The switching amplitude is controlled so that the feedback voltage FBN will be set to 0.2 V (Typ.). The start delay time can be set in the DLY1 pin at the time of startup. When the DLY2 voltage reaches 0.65 V (Typ.), switching waves will be output from the DRN pins. Over Voltage protection of the Boost Converter The boost converter has an overvoltage protection to protect the internal power MOS FET (SW) in case the feed back (FB) pin is floating or shorted to GND. Vs voltage is monitored with comparator over the OS pin. When the voltage of OS pin reached 19V (typ.), the Boost Converter stops its switching until the OS pin voltage falls below the comparator threshold.
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8/18
2009.07 - Rev.B
BD8160AEFV
Technical Note
Start-up Sequence The DC/DC converter of this IC incorporates a soft start function, and the charge pump incorporates a delay function, for which independent time settings are possible through external capacitors. As the capacitance, 0.01 F to 0.1 F is recommended. If the capacitance is set lower than 0.01 F, the overshooting may occur on the output voltage. If the capacitance is set larger than 0.1 F, the excessive back current flow may occur in the internal parasitic elements when the power is turned OFF and it may damage IC. When the capacitor more than 0.1 F is used, be sure to insert a diode to VIN in series, or a bypass diode between the SS and VIN pins.
Bypass diode Back current prevention diode
VIN
Fig.25 Example of Bypass Diode Use When there is the activation relation (sequences) with other power supplies, be sure to use the high-precision product (such as X5R). Soft start time may vary according to the input voltage, output loads, coils, voltage, and output capacitance. Be sure to verify the operation using the actual product. A delay of the charge pump starts from a point where VLOGIC reaches 85% of its nominal value (Typ.). Soft start time of DC/DC converter block: tss Delay time of charge pump block: t DELAY Tss = (Css x 0.6 V) / 10 A [s] t DELAY = (Css x0.65) / 5 A [s] Where, Css is an external capacitor. Where, Css is an external capacitor. Startup example
EN2 EN1
Vin VLOGIC DLY2 VGH Vs
DLY1
VGL
GD
Fig. 26 Output Timing Sequence with EN2 always high (EN2=VIN)
EN2 EN1
Vin VLOGIC DLY2 VGH Vs
DLY1
VGL
GD
Fig. 27 Output Timing Sequence(with using EN1 and EN2)
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9/18
2009.07 - Rev.B
BD8160AEFV
Technical Note
Short Circuit Protection BD8160AEFV has a short circuit protection feature to prevent the large current flowing when the output is shorted to GND. This function is monitoring VS, VLOGIC, VGH and VGL voltage and starts the timer when at least one of the outputs is not operating properly (when the output voltage was lower than expected) After TBD ms (Typ) of this abnormal state, BD8160AEFV will shutdown the all outputs and latch the state. The timer operation will be done even when BD8160AEFV starts up. Therefore, please adjust the capacitor for SS, DLY1 and DLY2 (Softstart and Delaystart) so that the all output voltage reach the expected value within the Short Circuit Protection Time (TBD ms Typ)
VS FB
+
-
219 / 328 ms (typ) Counter
219 / 328 ms (Typ) of this abnormal state, BD8160AEFV will shutdown the all outputs and latch the state.
Reset VLOGIC FBB
ALL SHUTDOWN & LATCH
+
VIN VGH FBP VS
92% detection
-
VS is shorted to GND
84% detection
VLOGIC is shorted
+
VLOGIC
80% detection
-
to GND 82% detection 72% detection
70% detection
VGH
VGH,VGL are shorted
+
to GND
-
VGL
80% detection 70% detection
Start Up time
Short Circuit Protection Time
(Start up time should be less than Short Circuit Protection Time)
Fig. 28
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10/18
2009.07 - Rev.B
BD8160AEFV
Technical Note
Selecting Application Components (1) Output LC constant (Boost Converter) The inductance L to use for output is decided by the rated current ILR and input current maximum value IOMAX of the inductance.
IL IOMAX + IL should not reach the rated value level ILR IOMAX mean current t
VCC
IL
Vo
L
Co
Fig. 29 Fig. 30 Adjust so that IOMAX + IL does not reach the rated current value ILR. At this time, IL can be obtained by the following equation. 1 Vo-Vcc 1 Vcc [A] IL = L Vo f Set with sufficient margin because the inductance L value may have the dispersion of 30%. For the capacitor C to use for the output, select the capacitor which has the larger value in the ripple voltage VPP permissible value and the drop voltage permissible value at the time of sudden load change. Output ripple voltage is decided by the following equation. 1 Vcc IL = ILMAX RESR + ( ILMAX ) [V] VPP fCo Vo 2 Perform setting so that the voltage is within the permissible ripple voltage range. For the drop voltage VDR during sudden load change, please perform the rough calculation by the following equation. I 10 s [V] VDR = Co However, 10 s is the rough calculation value of the DC/DC response speed. Make Co settings so that these two values will be within the limit values. (2) Output LC constant (Buck Converter) The inductance L to use for output is decided by the rated current ILR and input current maximum value IOMAX of the inductance.
IL IOMAX + IL should not reach the rated value level ILR IOMAX mean current t
VCC
IL L Co
Vo
Fig. 31
Fig. 32
Adjust so that IOMAX + IL does not reach the rated current value ILR. At this time, IL can be obtained by the following equation. 1 Vo 1 (Vcc - Vo) IL = [A] L Vcc f Set with sufficient margin because the inductance L value may have the dispersion of 30%. For the capacitor C to use for the output, select the capacitor which has the larger value in the ripple voltage VPP permissible value and the drop voltage permissible value at the time of sudden load change. Output ripple voltage is decided by the following equation. Vo 1 IL [V] = IL RESR + VPP 2Co Vcc f Perform setting so that the voltage is within the permissible ripple voltage range. For the drop voltage VDR during sudden load change, please perform the rough calculation by the following equation. I VDR = 10 s [V] Co However, 10 s is the rough calculation value of the DC/DC response speed. Make Co settings so that these two values will be within the limit values.
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11/18
2009.07 - Rev.B
BD8160AEFV
Technical Note
(3) Phase compensation Phase Setting Method The following conditions are required in order to ensure the stability of the negative feedback circuit. Phase lag should be 150 or lower during gain 1 (0 dB) (phase margin of 30 or higher). Because DC/DC converter applications are sampled using the switching frequency, the overall GBW should be set to 1/10 the switching frequency or lower. The target application characteristics can be summarized as follows: Phase lag should be 150 or lower during gain 1 (0 dB) (phase margin of 30 or higher). The GBW at that time (i.e., the frequency of a 0-dB gain) is 1/10 of the switching frequency or below. In other words, because the response is determined by the GBW limitation, it is necessary to use higher switching frequencies to raise response. One way to maintain stability through phase compensation involves canceling the secondary phase lag (-180) caused by LC resonance with a secondary phase advance (by inserting 2 phase advances). The GBW (i.e., the frequency with the gain set to 1) is determined by the phase compensation capacitance connected to the error amp. Increase the capacitance if a GBW reduction is required. (a) Standard integrator (low-pass filter) (b) Open loop characteristics of integrator
A Gain [dB]
(a) -20 dB/decade GBW(b)
Feedback R
A FB C
COMP
0 F 0 Phase -90 [] -180 -90 Phase margin -180 F
Fig. 33 Point (a) fa = 1 2RCA [Hz] Point (b) fb = GBW =
Fig. 34 1 2RC [Hz]
The error amp performs phase compensation of types (a) and (b), making it act as a low-pass filter. For DC/DC converter applications, R refers to feedback resistors connected in parallel. From the LC resonance of output, the number of phase advances to be inserted is two.
Vo R1 C1
LC resonant frequency fp =
1 2LC 1 2C1R1 1 2C2R3
[Hz]
R2
A
COMP C2 R3
Phase advance
fz1 =
[Hz]
Phase advance
fz2 =
[Hz]
Fig. 35 Set a phase advancing frequency close to the LC resonant frequency for the purpose of canceling the LC resonance.
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12/18
2009.07 - Rev.B
BD8160AEFV
(4) Design of Feedback Resistance constant Set the feedback resistance as shown below.
Technical Note
VS VLOGIC
R1 R2 FB FBB
Reference voltage (FB:1.162V FBB:1.213V)
ERR
VS, VLOGIC =
R1 + R2 R2
Reference Voltage
[V]
Fig. 36 (5) Positive-side Charge Pump Settings The IC incorporates a charge pump controller, thus making it possible to generate stable gate voltage. The output voltage is determined by the following equation. As the setting range, 10k to 330k is recommended. If the resistor is set lower than 10k, it causes reduction of power efficiency. If it is set more than 330k, the offset voltage becomes larger by the input bias current of 0.1A (Typ.) in the internal error amp. Vo2 R6 R7 Fig. 37 By connecting capacitance to the DLY2 pin, the rising delay time can be set for the positive-side charge pump output. The delay time is determined by the following equation. Delay time of charge pump block t DELAY t DELAY = (CDLS 0.65) / 5 A [s] Where, CDLS is an external capacitor. (6) Negative-side Charge Pump Settings BD8160AEFV incorporates a charge pump controller for negative voltage, thus making it possible to generate stable gate voltage. The output voltage is determined by the following equation. As the setting range, 10k to 330k is recommended. If the resistor is set lower than 10k, it causes reduction of power efficiency. If it is set more than 330k, the offset voltage becomes larger by the input bias current of 0.1A (Typ.) in the internal error amp. VGL R8 R9 FBN REF 1.213V Fig.38 Like the positive-side charge pump, the rise delay time can be set by connecting capacitance to the DLY1 pin. 0.2V

Reference voltage 1.213V
FBP
ERR
Vo2 =
R6 + R7 R7
Reference Voltage
[V]
ERR
VGL =
-
R8 R9
1.013 + 0.2 V
[V]
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13/18
2009.07 - Rev.B
BD8160AEFV
Selecting the Feedforward Capacitor (Boost Converter) Across the upper resistor R1, a bypass capacitor is needed to have a stable converter loop. C1 will set a zero in the loop together with R1.
Technical Note
L=10H
R1
C1 C1 =
1 2fz1R1 Fz1=11kHz @L=10H
COMP
C2
R2
Fig.39
The regulator loop can be compensated by adjusting the exfernal components connected to the COMP pin. C2,R2 are decided by the following formula. Fz1=11kHZ = 1 2C2R2
Selecting the Feedforward Capacitor (Buck converter) The feedforward capacitor across the upper feedback resistor divider sets a zero in the control loop.
L=l0H C3 = R3 C3
1 2fz2R3 Fz2=12kHz @L=10H
FBB
Fig.40
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14/18
2009.07 - Rev.B
BD8160AEFV
I/O Equivalent Circuit Diagram 18.SWB
Vcc PVcc REG
Technical Note
17.BOOT
25.DLY1 26.DLY2 28.SS
Vcc
SW
2.COMP 24.REF
1.FB
13.FBN 14.FBP 15.FBB
VR
27.GD
VR
Vcc
9.EN2 12.FREQ 16.EN1
10.DRP 11.DRN
Vo1
4.SW
5.SW
3.OS
Fig.41
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15/18
2009.07 - Rev.B
BD8160AEFV
Technical Note
Notes for use 1) Absolute maximum ratings Use of the IC in excess of absolute maximum ratings such as the applied voltage or operating temperature range may result in IC damage. Assumptions should not be made regarding the state of the IC (short mode or open mode) when such damage is suffered. A physical safety measure such as a fuse should be implemented when use of the IC in a special mode where the absolute maximum ratings may be exceeded is anticipated. 2) GND potential Ensure a minimum GND pin potential in all operating conditions. 3) Setting of heat Use a thermal design that allows for a sufficient margin in light of the power dissipation (Pd) in actual operating conditions. 4) Pin short and mistake fitting Use caution when orienting and positioning the IC for mounting on printed circuit boards. Improper mounting may result in damage to the IC. Shorts between output pins or between output pins and the power supply and GND pins caused by the presence of a foreign object may result in damage to the IC. 5) Actions in strong magnetic field Use caution when using the IC in the presence of a strong magnetic field as doing so may cause the IC to malfunction. 6) Testing on application boards When testing the IC on an application board, connecting a capacitor to a pin with low impedance subjects the IC to stress. Always discharge capacitors after each process or step. Ground the IC during assembly steps as an antistatic measure, and use similar caution when transporting or storing the IC. Always turn the IC's power supply off before connecting it to or removing it from a jig or fixture during the inspection process. 7) Ground wiring patterns When using both small signal and large current GND patterns, it is recommended to isolate the two ground patterns, placing a single ground point at the application's reference point so that the pattern wiring resistance and voltage variations caused by large currents do not cause variations in the small signal ground voltage. Be careful not to change the GND wiring patterns of any external components. 8) Regarding input pin of the IC This monolithic IC contains P+ isolation and P substrate layers between adjacent elements in order to keep them isolated. P/N junctions are formed at the intersection of these P layers with the N layers of other elements to create a variety of parasitic elements. For example, when the resistors and transistors are connected to the pins as shown in Fig.42, a parasitic diode or a transistor operates by inverting the pin voltage and GND voltage. The formation of parasitic elements as a result of the relationships of the potentials of different pins is an inevitable result of the IC's architecture. The operation of parasitic elements can cause interference with circuit operation as well as IC malfunction and damage. For these reasons, it is necessary to use caution so that the IC is not used in a way that will trigger the operation of parasitic elements such as by the application of voltages lower than the GND (P substrate) voltage to input and output pins.
Resistor (Pin A) (Pin B) C Transistor (NPN) (Pin B) B C E GND Parasitic elements N (Pin A) Parasitic elements GND

B
GND P+ N N P N Parasitic elements GND Parasitic elements N P N P+ P+ N P substrate GND P P+

E
Fig. 42 Example of a Simple Monolithic IC Architecture 9) Overcurrent protection circuits An overcurrent protection circuit designed according to the output current is incorporated for the prevention of IC damage that may result in the event of load shorting. This protection circuit is effective in preventing damage due to sudden and unexpected accidents. However, the IC should not be used in applications characterized by the continuous operation or transitioning of the protection circuits. At the time of thermal designing, keep in mind that the current capacity has negative characteristics to temperatures. 10) Thermal shutdown circuit (TSD) This IC incorporates a built-in TSD circuit for the protection from thermal destruction. The IC should be used within the specified power dissipation range. However, in the event that the IC continues to be operated in excess of its power dissipation limits, the attendant rise in the chip's junction temperature Tj will trigger the TSD circuit to turn off all output power elements. Operation of the TSD circuit presumes that the IC's absolute maximum ratings have been exceeded. Application designs should never make use of the TSD circuit. 11) Testing on application boards At the time of inspection of the installation boards, when the capacitor is connected to the pin with low impedance, be sure to discharge electricity per process because it may load stresses to the IC. Always turn the IC's power supply off before connecting it to or removing it from a jig or fixture during the inspection process. Ground the IC during assembly steps as an antistatic measure, and use similar caution when transporting or storing the IC. 12) EN1 terminal EN1 terminal should be pulled up to VIN terminal.
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16/18
2009.07 - Rev.B
BD8160AEFV
Power Dissipation POWER DISSIPATION: PD [mW]
Technical Note
On 70 70 1.6 mm glass epoxy PCB
5000 4000 3000 2000 1000
(4)4700mW (3)3300mW (2)1850mW (1)1450mW
(1) 1-layer board (Backside copper foil area 0 mm 0 mm) (2) 2-layer board (Backside copper foil area 15 mm 15 mm) (3) 2-layer board (Backside copper foil area 70 mm 70 mm) (4) 4-layer board (Backside copper foil area 70 mm 70 mm)
0 0 25 50 75 100 125 150 AMBIENT TEMPERATURE: Ta [C] Fig. 43
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17/18
2009.07 - Rev.B
BD8160AEFV
Ordering part number
Technical Note
B
D
8
Part No.
1
6
0
A
E
F
V
-
E
2
Part No.
Package EFV : HTSSOP-B28
Packaging and forming specification E2: Embossed tape and reel
HTSSOP-B28
9.70.1 (MAX 10.05 include BURR) (5.5)
28 15

Tape
+6 4 -4
0.50.15 1.00.2
Embossed carrier tape (with dry pack) 2500pcs E2
The direction is the 1pin of product is at the upper left when you hold
Quantity Direction of feed
6.40.2
4.40.1
(2.9)
( reel on the left hand and you pull out the tape on the right hand
)
1
14
0.625
1.0MAX
1PIN MARK S
+0.05 0.17 -0.03
0.850.05
0.080.05
0.08 S 0.65 +0.05 0.24 -0.04 0.08
M
1pin
Direction of feed
(Unit : mm)
Reel
Order quantity needs to be multiple of the minimum quantity.
www.rohm.com (c) 2009 ROHM Co., Ltd. All rights reserved.
18/18
2009.07 - Rev.B
Notice
Notes
No copying or reproduction of this document, in part or in whole, is permitted without the consent of ROHM Co.,Ltd. The content specified herein is subject to change for improvement without notice. The content specified herein is for the purpose of introducing ROHM's products (hereinafter "Products"). If you wish to use any such Product, please be sure to refer to the specifications, which can be obtained from ROHM upon request. Examples of application circuits, circuit constants and any other information contained herein illustrate the standard usage and operations of the Products. The peripheral conditions must be taken into account when designing circuits for mass production. Great care was taken in ensuring the accuracy of the information specified in this document. However, should you incur any damage arising from any inaccuracy or misprint of such information, ROHM shall bear no responsibility for such damage. The technical information specified herein is intended only to show the typical functions of and examples of application circuits for the Products. ROHM does not grant you, explicitly or implicitly, any license to use or exercise intellectual property or other rights held by ROHM and other parties. ROHM shall bear no responsibility whatsoever for any dispute arising from the use of such technical information. The Products specified in this document are intended to be used with general-use electronic equipment or devices (such as audio visual equipment, office-automation equipment, communication devices, electronic appliances and amusement devices). The Products specified in this document are not designed to be radiation tolerant. While ROHM always makes efforts to enhance the quality and reliability of its Products, a Product may fail or malfunction for a variety of reasons. Please be sure to implement in your equipment using the Products safety measures to guard against the possibility of physical injury, fire or any other damage caused in the event of the failure of any Product, such as derating, redundancy, fire control and fail-safe designs. ROHM shall bear no responsibility whatsoever for your use of any Product outside of the prescribed scope or not in accordance with the instruction manual. The Products are not designed or manufactured to be used with any equipment, device or system which requires an extremely high level of reliability the failure or malfunction of which may result in a direct threat to human life or create a risk of human injury (such as a medical instrument, transportation equipment, aerospace machinery, nuclear-reactor controller, fuel-controller or other safety device). ROHM shall bear no responsibility in any way for use of any of the Products for the above special purposes. If a Product is intended to be used for any such special purpose, please contact a ROHM sales representative before purchasing. If you intend to export or ship overseas any Product or technology specified herein that may be controlled under the Foreign Exchange and the Foreign Trade Law, you will be required to obtain a license or permit under the Law.
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